Integrated circuit fabrication methods have reached a point where many hundreds of millions of transistors are routinely formed on a single chip. Each new generation of fabrication techniques and equipment are allowing commercial scale fabrication of ever smaller and faster transistors, but also increase the difficulty to make even smaller, faster circuit elements. The shrinking dimensions of circuit elements, now well below the 50 nm threshold, has caused chip designers to look for new low-resistivity conductive materials and new low-dielectric constant (i.e., low-k) insulating materials to improve (or simply maintain) the electrical performance of the integrated circuit.
Parasitic capacitance becomes a significant impediment to transistor switching rate as the number of transistors per area is increased. Capacitance exists between all adjacent electrically isolated conductors within an integrated circuit and may limit the switching rate regardless of whether the conducting portions are at the “front end” or the “back end” of the manufacturing process flow.
Thus, there is a need for new techniques and materials to form low-k material between adjacent conductors. One class of materials used to provide low-k separation between conductors is oxidized organo-silane films, such as the Black Diamond films commercially available from Applied Materials, Inc. of Santa Clara, Calif. These films have lower dielectric constants (e.g., about 3.5 or less) than conventional spacer materials like silicon oxides and nitrides. Unfortunately, some new processes involve exposing low-k films to environments which can increase the effective dielectric constant and limit device performance.
Thus there is a need for new processes which maintain a lower effective dielectric constant following exposure of a low-k film to these environments.